1. Field
The present invention generally relates to error-detection and error-correction techniques for computer memories. More specifically, the present invention relates to a computer memory system that uses an error-correcting code for a data block to additionally detect corruption of an address associated with the data block.
2. Related Art
Computer systems routinely use error-detecting and error-correcting codes to detect and/or correct various data errors which are caused, for example, by noisy communication channels and unreliable storage media. Some error-detecting and error-correcting codes, such as single-error correction, double-error detection (SECDED) Hamming codes, can be used to correct single-bit errors and detect double-bit errors. Other codes, which are based on Galois fields, can be used to correct a special class of multi-bit errors caused by a failure of an entire memory component. (For example, see U.S. Pat. No. 7,188,296, entitled “ECC for Component Failures Using Galois Fields,” by inventor Robert E. Cypher, filed 30 Oct. 2003, referred to as “the '296 patent.”)
Although such memory systems go to great lengths to detect and correct “data” errors, they typically do little or nothing to detect “address” errors which can arise when an address is communicated to a memory device during a memory operation. For example, such address errors can be caused by noisy communication channels, or timing problems that occur when latching an address in a temporary register while the address is in transit to the memory. Such address errors can be just as problematic as data errors, because address errors can cause a data block to be read from and/or written to the wrong memory address.
Hence, what is needed is a method and an apparatus for using error-correcting codes to detect such address errors.